View CY2834605_4544373.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY28346
Clock Synthesizer with Differential CPU Outputs
Features
* Compliant with Intel(R) CK 408 Mobile Clock Synthesizer specifications * 3.3V power supply * Three differential CPU clocks * Ten copies of PCI clocks Table 1. Frequency Table S2 1 1 1 1 0 0 0 0 M M S1 0 0 1 1 0 0 1 1 0 0 S0 0 1 0 1 0 1 0 1 0 1
[1]
* 5/6 copies of 3V66 clocks * SMBus support with read-back capabilities * Spread Spectrum electromagnetic interference (EMI) reduction * Dial-a-FrequencyTM features * Dial-a-dBTM features * 56-pin TSSOP and SSOP packages
CPU (0:2) 66M 100M 200M 133M 66M 100M 200M 133M Hi-Z TCLK/2
3V66 66M 66M 66M 66M 66M 66M 66M 66M Hi-Z TCLK/4
66BUFF(0:2)/ 3V66(0:4) 66IN 66IN 66IN 66IN 66M 66M 66M 66M Hi-Z TCLK/4
66IN/3V66-5 66-MHz clock input 66-MHz clock input 66-MHz clock input 66-MHZ clock input 66M 66M 66M 66M Hi-Z TCLK/4
PCI_FPCI 66IN/2 66IN/2 66IN/2 66IN/2 33 M 33 M 33 M 33 M Hi-Z TCLK/8
REF 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M 14.318M Hi-Z TCLK
USB/ DOT 48M 48M 48M 48M 48M 48M 48M 48M Hi-Z TCLK/2
Block Diagram
XIN XOUT PLL1 CPU_STP# IREF VSSIREF S(0:2) MULT0 VTT_PG# PCI_STP# PLL2 WD Logic I2C Logic Power Up Logic
/2
Pin Configuration
REF CPUT(0:2) CPUC(0:2)
VDD XIN XOUT VSS PCIF0 PCIF1 PCIF2 VDD VSS PCI0 PCI1 PCI2 PCI3 VDD VSS PCI4 PCI5 PCI6 VDD VSS 66B0/3V66_2 66B1/3V66_3 66B2/3V66_4 66IN/3V66_5 PD# VDDA VSSA VTT_PG# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF S1 S0 CPU_STP# CPUT0 CPUC0 VDD CPUT1 CPUC1 VSS VDD CPUT2 CPUC2 MULT0 IREF VSSIREF S2 48MUSB 48MDOT VDD VSS 3V66_1/VCH PCI_STP# 3V66_0 VDD VSS SCLK SDATA
3V66_0 3V66_1/VCH PCI(0:6) PCI_F(0:2) 48M USB 48M DOT
CY28346
PD# SDATA SCLK VDDA
66B[0:2]/3V66[2:4] 66IN/3V66-5
Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a 0 state will be latched into the device's internal state register.
Cypress Semiconductor Corporation Document #: 38-07331 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised March 11, 2005
CY28346
Pin Description
Pin 2 3 52, 51, 49, 48, 45, 44 10, 11, 12, 13, 16, 17, 18 5, 6, 7 Name XIN XOUT CPUT(0:2), CPUC(0:2) PCI(0:6) PCIF (0:2) PWR VDD VDD VDDP VDD VDD VDD VDD VDD48 VDD48 VDD VDD VDD I/O I O O O O Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. Differential Host Output Clock Pairs. See Table 1 for frequency/functionality. PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See Table 1. 33-MHz PCI Clocks. /2 copies of 66IN or 3V66 clocks that may be free running (not stopped when PCI_STP# is asserted LOW) or may be stoppable depending on the programming of SMBus register Byte3,Bits (3:5). Buffered Output Copy of the Device's XIN Clock. Current Reference Programming Input for CPU Buffers. A resistor is connected between this pin and VSSIREF. Qualifying Input that Latches S(0:2) and MULT0. When this input is at a logic LOW, the S(0:2) and MULT0 are latched. Fixed 48-MHz USB Clock Outputs. Fixed 48-MHZ DOT Clock Outputs. 3.3V 66-MHz Fixed-frequency Clock. 3.3V Clock Selectable with SMBus Byte0,Bit5, When Byte5,Bit5. When Byte 0,Bit 5 is at a logic 1, then this pin is a 48M output clock. When Byte0,Bit5 is a logic 0, this is a 66M output clock (default). Power-down Mode Pin. A logic LOW level causes the device to enter a power-down state. All internal logic is turned off except for the SMBus logic. All output buffers are stopped. Programming Input Selection for CPU Clock Current Multiplier.
56 42 28 39 38 33 35
REF IREF VTT_PG# 48MUSB 48MDOT 3V66_0 3V66_1/VCH
O I I O O O O
25
PD#
I PU I PU I I
43 55, 54 29
MULT0 S(0,1) SDATA I I
30 40 34
SCLK S2 PCI_STP#
I VDD VDD
53
CPU_STP#
VDD VDD VDD
24 21, 22, 23 1, 8, 14, 19, 32, 37, 46, 50 4, 9, 15, 20, 27, 31, 36, 47 41
66IN/3V66_5 66B(0:2)/ 3V66(2:4) VDD VSS VSSIREF VDDA
Frequency Select Inputs. See Table 1. Serial Data Input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. I Serial Clock Input. Conforms to the SMBus specification. I Frequency Select Input. See Table 1. This is a Tri-level input which is driven T HIGH, LOW or driven to a intermediate level. I PCI Clock Disable Input. When asserted LOW, PCI (0:6) clocks are synchroPU nously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks' outputs if they are programmed to be PCIF clocks via the device's SMBus interface. I CPU Clock Disable Input. When asserted LOW, CPUT (0:2) clocks are PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchronously disabled in a LOW state. I/O Input Connection for 66CLK(0:2) Output Clock Buffers if S2 = 1, or output clock for fixed 66-MHz clock if S2 = 0. See Table 1. O 3.3V Clock Outputs. These clocks are buffered copies of the 66IN clock or fixed at 66 MHz. See Table 1. PWR 3.3V Power Supply. PWR Common Ground. PWR Current Reference Programming Input for CPU Buffers. A resistor is connected between this pin and IREF. This pin should also be returned to device VSS. PWR Analog Power Input. Used for phase-locked loops (PLLs) and internal analog circuits. It is also specifically used to detect and determine when power is at an acceptable level to enable the device to operate. Page 2 of 20
26
-
Document #: 38-07331 Rev. *C
CY28346
Two-Wire SMBus Control Interface
The two-wire control interface implements a Read/Write slave only interface according to SMBus specification. The device will accept data written to the D2 address and data may read back from address D3. It will not respond to any other addresses, and previously set control registers are retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional bytes must be sent: 1. "Command code" byte 2. "Byte count" byte. Although the data (bits) in the command is considered "don't care," it must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged.
Byte 0: CPU Clock Register[2,3] Bit 7 6 @Pup 0 0 Pin# Description Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On This is a Read and Write control bit. CPU Clock Power-down Mode Select. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) LOW when PD# is asserted LOW. 1 = Tri-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to CPU_STP#. 35 3V66_1/VCH Frequency Select, 0 = 66M selected, 1 = 48M selected This is a Read and Write control bit.
5 4 3 2 1 0
0 Pin 53 Pin 34 Pin 40 Pin 55 Pin 54
44,45,48,49,5 CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is 1,52 Read-only. 10,11,12,13,16 Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# ,17,18 is a logical AND function of the internal SMBus register bit and the external PCI_STP# pin. Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only. Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only. Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.
Byte 1: CPU Clock Register Bit 7 6 @Pup Pin 43 0 Pin# 43 53 Description MULT0 (Pin 43) Value. This bit is Read-only. CPUT/C(0:2) Output Functionality Control When CPU_STP# is Asserted. 0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) LOW when CPU_STP# asserted LOW. 1 = three-state all CPU outputs. This bit will override Byte0,Bit6 such that even if it is 0, when PD# goes LOW the CPU outputs will be three-stated. CPU2 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit. CPU1 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit. CPUT0 Functionality Control When CPU_STP# is Asserted LOW. 1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW. This is a Read and Write control bit. CPUT/C2 Output Control. 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW. This is a Read and Write control bit. CPUT/C1 Output Control. 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW. This is a Read and Write control bit. CPUT/C0 Output Control. 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW. This is a Read and Write control bit.
5 4 3 2 1 0
0 0 0 1 1 1
44,45 48,49 51,52 44,45 48,49 51,52
Notes: 2. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 - 1.8V and HIGH = > 2.0V. 3. The "Pin#" column lists the relevant pin number where applicable. The "@Pup" column gives the default state at power-up.
Document #: 38-07331 Rev. *C
Page 3 of 20
CY28346
Byte 2: PCI Clock Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Pin# 53 18 17 16 13 12 11 10 Description REF Output Control. 0 = high strength, 1 = low strength. PCI6 Output Control. 1 = enabled, 0 = forced LOW. PCI5 Output Control. 1 = enabled, 0 = forced LOW. PCI4 Output Control. 1 = enabled, 0 = forced LOW. PCI3 Output Control. 1 = enabled, 0 = forced LOW. PCI2 Output Control. 1 = enabled, 0 = forced LOW. PCI1 Output Control. 1 = enabled, 0 = forced LOW. PCI0 Output Control. 1 = enabled, 0 = forced LOW.
Byte 3: PCI_F Clock and 48M Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 0 1 1 1 Pin# 38 39 7 6 5 7 6 5 Description 48MDOT Output Control. 1 = enabled, 0 = forced LOW. 48MUSB Output Control. 1 = enabled, 0 = forced LOW. PCI_STP#, Control of PCI_F2. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW. PCI_STP#, Control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW. PCI_STP#, Control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW. PCI_F2 Output Control. 1 = running, 0 = forced LOW. PCI_F1 Output Control. 1 = running, 0 = forced LOW. PCI_F0 Output Control. 1 = running, 0 = forced LOW.
Byte 4: DRCG Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 1 1 1 1 1 33 35 24 23 22 21 Pin# Reserved. Set = 0. 3V66_0 Output Enabled. 1 = enabled, 0 = disable. 3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled. 3V66_5 Output Enable. 1 = enabled, 0 = disabled. 66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled. 66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled. 66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled. Description SS2 Spread Spectrum Control Bit (0 = down spread, 1 = center spread).
Byte 5: Clock Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 0 0 0 Pin# SS1 Spread Spectrum Control Bit. SS0 Spread Spectrum Control Bit. 66IN to 66M delay Control MSB. 66IN to 66M delay Control LSB. Reserved. Set = 0. 48MDOT Edge Rate Control. When set to 1, the edge is slowed by 15%. Reserved. Set = 0. USB edge rate control. When set to 1, the edge is slowed by 15%. Description
Document #: 38-07331 Rev. *C
Page 4 of 20
CY28346
Byte 6: Silicon Signature Register[4] (all bits are Read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 0 0 1 1 Vendor Code = 0011 Pin# Revision = 0001 Description
Byte 7: Reserved Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Pin# Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Description
Byte 8: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 N6, MSB N5 N4 N3 N2 N3 N0, LSB Name Reserved. Set = 0. These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description
Byte 9: Dial-a-Frequency Control Register R Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 R5, MSB R4 R3 R2 R1 R0 DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from DAF (SMBus) registers. Name Reserved. Set = 0. These bits are for programming the PLL's internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description
Note: 4. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
Document #: 38-07331 Rev. *C
Page 5 of 20
CY28346
Dial-a-Frequency Features
SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. P is a large-value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 2. Table 2. P Value S(1:0) 00 01 10 11 P 32005333 48008000 96016000 64010667 therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. Table 3 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Table 3. Spread Spectrum SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Center Center Center Center Spread% +0.00, -0.25 +0.00, -0.50 +0.00, -0.75 +0.00, -1.00 +0.13, -0.13 +0.25, -0.25 +0.37, -0.37 +0.50, -1.50
Dial-a-dB Features
SMBus Dial-a-dB feature is available in this device via Byte8 and Byte9.
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth
CPUT T PCB
Test and Measurement Set-up
For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
33.2 2p F
M easurem ent P oint
M U LT S E L CPUC T PCB
63.4
475 33.2 2 pF
M easurem ent P oint
63.4
220
Figure 1. 1.0V Test Load Termination
33
TPCB
49.9 2pF
VDD
CPUT
Measurement Point
MULTSEL
33
CPUC
49.9
TPCB
2pF
Measurement Point
475
Figure 2. 0.7V Test Load Termination Document #: 38-07331 Rev. *C Page 6 of 20
CY28346
Output under Test Probe Load Cap 3.3V signals
-
tDC 3.3V
-
2.4V
1.5V
0.4V 0V Tr Tf
Figure 3. For Single-ended Output Signals
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics The current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. The following parameters are used to specify output buffer characteristics: 1. Output impedance of the current mode buffer circuit--Ro (see Figure 4). 2. Minimum and maximum required voltage operation range of the circuit--Vop (see Figure 4).
3. Series resistance in the buffer circuit--Ros (see Figure 4). 4. Current accuracy at given configuration into nominal test load for given configuration. Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage at the pin of the device. The various output current configurations are shown in the host swing select functions table. For all configurations, the deviation from the expected output current is 7% as shown in the current accuracy table.
VDD3 (3.3V +/- 5%)
Ro Iout
Slope ~ 1/R0
Ros 0V Iout 1.2V
Vout = 1.2V max
Figure 4. Buffer Characteristics Table 4. Host Clock (HCSL) Buffer Characteristics Characteristic Document #: 38-07331 Rev. *C Min.
Vout
Max. Page 7 of 20
CY28346
Table 4. Host Clock (HCSL) Buffer Characteristics Ro Ros Vout Table 5. CPU Clock Current Select Function Mult0 0 1 Board Target Trace/Term Z 50 50 Reference R, Iref - Vdd (3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4*Iref Ioh = 6*Iref Voh @ Z 1.0V @ 50 0.7V @ 50 3000 (recommended) N/A N/A 1.2V
Table 6. Group Timing Relationship and Tolerances Description 3V66 to PCI 48MUSB to 48MDOT Skew 66B(0:2) to PCI offset Offset 2.5 ns 0.0 ns 2.5 ns Tolerance 1.0 ns 1.0 ns 1.0 ns Conditions 3V66 Leads PCI (unbuffered mode) 0 degrees phase shift 66B Leads PCI (buffered mode)
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is understood that the difference in edge rate will introduce some inherent offset. When 3V66_1/VCH clock is configured for VCH (48-MHz) operation it is also in phase with the USB and DOT outputs. See Figure 5.
66B(0:2) to PCI Buffered Clock Skew
Figure 7 shows the difference (skew) between the 3V33(0:5) outputs when the 66M clocks are connected to 66IN. This offset is described in the Group Timing Relationship and Tolerances section of this data sheet. The measurements were taken at 1.5V.
66IN to 66B(0:2) Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown in Figure 6. The Tpd is the prop delay from the input pin (66IN) to the output pins (66B[0:2]). The outputs' variation of Tpd is described in the AC parameters section of this data sheet. The measurement taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
Figure 8 shows the timing relationship between 3V66(0:5) and PCI(0:6) and PCI_F(0:2) when configured to run in the unbuffered mode.
48MUSB 48MDOT
Figure 5. 48MUSB and 48MDOT Phase Relationship
66IN
Tpd
66B(0:2)
Figure 6. 66IN to 66B(0:2) Output Delay Figure
66B(0:2) PCI(0:6) PCIF(0:2)
1.53.5ns
Figure 7. Buffer Mode - 33V66(0:1); 66BUF(0:2) Phase Relationship
Document #: 38-07331 Rev. *C
Page 8 of 20
CY28346
Special Functions
PCI_F and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. Any two of the PCI_F clock outputs can be used as IOAPIC 33 Mhz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event that these clocks are not required, they can be used as general PCI clocks or disabled via the assertion of the PCI_STP# pin. 3V66_1/VCH Clock Output The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. Configured as DRCG (66M), SMBus Byte0, Bit 5 = "0" The default condition for this pin is to power-up in a 66M operation. In 66M operation this output is SSCG-capable and when spreading is turned on, this clock will be modulated. Configured as VCH (48M), SMBus Byte0, Bit 5 = "1" In this mode, output is configured as a 48-Mhz non-spread spectrum output that is phase-aligned with other 48M outputs (USB and DOT) to within 1 ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power-on. When the SMBus Bit 5 of Byte 0 is programmed from a "0" to a "1," the 3V66_1/VCH output may glitch while transitioning to 48M output mode. CPU_STP# Clarification The CPU_STP# signal is an active LOW input used to synchronously stop and start the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# - Assertion When CPU_STP# pin is asserted, all CPUT/C outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two falling CPUT/C clock edges. The final state of the stopped CPU signals is CPUT = HIGH and CPU0C = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 "select") x (Iref), and the CPUC signal will not be driven. Due to external pull-down circuitry CPUC will be LOW during this stopped state. CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPUT/C outputs that were stopped to resume normal operation in a synchronous manner (meaning that no short or stretched clock pulses will be produces when the clock resumes). The maximum latency from the deassertion to active outputs is no more than two CPUC clock cycles.
Three-state Control of CPU Clocks Clarification
During CPU_STP# and PD# modes, CPU clock outputs may be set to driven or undriven (tri-state) by setting the corresponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
3V66(0:5) PCI(0:6) PCI_F(0:2)
Tpci
Figure 8. Unbuffered Mode - 3V66(0:5) to PCI (0:6) and PCI_F(0:2) Phase Relationship
CPU_STP# CPUT CPUC CPUT CPUC
Figure 9. CPU_STP# Assertion Waveform Document #: 38-07331 Rev. *C Page 9 of 20
CY28346
PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see Figure 14.) The PCI_F (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running.
CPU_STP# CPUT CPUC CPUT CPUC
Figure 10. CPU_STP# Deassertion Waveform Table 7. Cypress Clock Power Management Truth Table B0b6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B1b6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PD# 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 CPU_STP# 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Stoppable CPUT Running Iref x6 Iref x2 Iref x2 Running Hi-Z Hi-Z Hi-Z Running Iref x6 Hi-Z Hi-Z Running Hi-Z Hi-Z Hi-Z Stoppable CPUC Running Iref x6 LOW LOW Running Hi-Z Hi-Z Hi-Z Running Iref x6 Hi-Z Hi-Z Running Hi-Z Hi-Z Hi-Z Non-Stop CPUT Non-Stop CPUC Running Running Iref x2 Iref x2 Running Running Hi-Z Hi-Z Running Running Hi-Z Hi-Z Running Running Hi-Z Hi-Z Running Running LOW LOW Running Running Hi-Z Hi-Z Running Running Hi-Z Hi-Z Running Running Hi-Z Hi-Z
Document #: 38-07331 Rev. *C
Page 10 of 20
CY28346
PCI_STP# - Deassertion (transition from logic "0" to logic "1") The deassertion of the PCI_STP# signal will cause all PCI(0:6) and stoppable PCI_F(0:2) clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a HIGH level. Note. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus Byte 0,Bit 3. These two inputs to the function are logically AND'ed. If either the external pin or the internal SMBus register bit is set LOW, the stoppable PCI clocks will be stopped in a logic LOW state. Reading SMBus Byte 0,Bit 3 will return a 0 value if either of these control bits are set LOW (which indicates that the devices stoppable PCI clocks are not running). PD# (Power-down) Clarification The PD# (power-down) pin is used to shut off all clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is LOW, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the LOW "stopped" state. PD# - Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 x Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. PD# - Deassertion The power-up latency between PD# rising to a valid logic `1' level and the starting of all clocks is less than 3.0 ms.
t setup
PCI_STP# PCI_F(0:2) 33M PCI(0:6) 33M
Figure 11. PCI_STP# Assertion Waveform
t setup
PCI_STP# PCI_F(0:2) PCI(0:6)
Figure 12. PCI_STP# Deassertion Waveform
Document #: 38-07331 Rev. *C
Page 11 of 20
CY28346
66Buff[0..2] PCIF PW RDW N# CPU 133MHz CPU# 133MHz 3V66 66In USB 48MHz REF 14.318MHz
Figure 13. Power-down Assertion Timing Waveforms Figure--Buffered Mode
PWRDWN# CPUT(0:2) 133MHz CPUC(0:2) 133MHz PCI 33MHz 3V66 USB 48MHz REF 14.318MHz
Figure 14. Power-down Assertion Timing Waveforms--Unbuffered Mode
Document #: 38-07331 Rev. *C
Page 12 of 20
CY28346
30uS min 400uS max
<1.8mS
66Buff1 / GMCH 66Buff[0,2] PCIF / APIC 33MHz PCI 33MHz PW RDW N# CPU 133MHz CPU# 133MHz 3V66 66In USB 48MHz REF 14.318MHz
Figure 15. Power-down Deassertion Timing Waveforms--Buffered Mode Table 8. PD# Functionality PD# 1 0 DRCG 66M LOW 66CLK (0:2) 66Input LOW PCI_F/PCI 66Input/2 LOW PCI 66Input/2 LOW USB/DOT 48M LOW
Document #: 38-07331 Rev. *C
Page 13 of 20
CY28346
Maximum Ratings[5]
Input Voltage Relative to VSS:.............................. VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature:.................................... 0C to +85C Maximum Power Supply:................................................ 3.5V
Current Accuracy[6]
Parameter Iout Iout Conditions VDD = nominal (3.30V) VDD = 3.30 5% Configuration M0 = 0 or 1 and Rr (see Table 1) All combinations of M0 or 1 and Rr (see Table 1) Load Nominal test load for given configuration Nominal test load for given configuration Min. Max. -7% + 7% Inom Inom -12% + 12% Inom Inom
DC Parameters (VDD = VDDA = 3.3V 5%, TA = 0C to +70C)
Parameter IDD3.3V IPD3.3V CIN COUT LPIN CXTAL Description Dynamic Supply Current Power-down Supply Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance Measured from the XIN or XOUT pin to ground 30 36 Conditions All frequencies at maximum values PD# asserted
[7]
Min.
Typ.
Max. 280 Note 8 5 6 7 42
Unit mA mA pF pF nH pF
AC Parameters (VDD = VDDA = 3.3V 5%, TA = 0C to +70C)
66 MHz Parameter Crystal TDC TPERIOD VHIGH VLOW TR / TF TCCJ Description XIN Duty Cycle XIN period XIN HIGH Voltage XIN LOW Voltage XIN Rise and Fall Times XIN Cycle to Cycle Jitter Min. 47.5 69.84 0.7VDD 0 Max. 52.5 71.0 VDD 0.3VDD 10.0 500 100 MHz Min. 47.5 69.84 0.7VDD 0 Max. 52.5 71.0 VDD 0.3VDD 10.0 500 133 MHz Min. 47.5 69.84 0.7VDD 0 Max. 52.5 71.0 VDD 0.3VDD 10.0 500 200 MHz Min. 47.5 69.84 0.7VDD 0 Max. 52.5 71.0 VDD 0.3VDD 10.0 500 Unit % ns V V ns ps 14 12, 15, 10 15, 16, 19 15, 16, 19 12, 15, 16 Notes 9, 10, 11 9, 12, 13, 10
CPU at 0.7V Timing TDC CPUT and CPUC Duty Cycle TPERIOD TSKEW CPUT and CPUC Period Any CPU to CPU Clock Skew
45 14.85
55 15.3 100
45 9.85
55 10.2 100
45 7.35
55 7.65 100
45 4.85
55 5.1 100
% ns ps
Notes: 5. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. Inom refers to the expected current based on the configuration of the device. 7. All outputs loaded as per maximum capacitive load table. 8. Absolute value = ((Programmed CPU Iref) x (2)) + 10 mA. 9. This parameter is measured as an average over 1 s duration, with a crystal center frequency of 14.31818 MHz. 10. When Xin is driven from an external clock source. 11. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. 12. All outputs loaded as perTable 9 below. 13. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet). 14. Measured between 0.2VDD and 0.7VDD. 15. This measurement is applicable with Spread ON or Spread OFF. 16. Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0V Measured from VOL = 0.175V to VOH = 0.525V. 17. Measured from VOL = 0.175V to VOH = 0.525V. 18. Determined as a fraction of 2*(Trise-Tfall)/ (Trise+Tfall). 19. Test load is Rta = 33.2, Rd = 49.9.
Document #: 38-07331 Rev. *C
Page 14 of 20
CY28346
AC Parameters (VDD = VDDA = 3.3V 5%, TA = 0C to +70C) (continued)
66 MHz Parameter TCCJ TR/TF Description CPU Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Rise/Fall Matching DeltaTR DeltaTF VCROSS Rise Time Variation Fall Time Variation Crossing Point Voltage at 0.7V Swing 280 175 Min. Max. 150 700 20% 125 125 430 280 175 100 MHz Min. Max. 150 700 20% 125 125 430 280 175 133 MHz Min. Max. 150 700 20% 125 125 430 280 175 200 MHz Min. Max. 150 700 20% 125 125 430 ps ps mV Unit ps ps Notes 15, 16, 19 15, 17, 20 17, 18, 19 17, 19 17, 19 15, 19
CPU at 1.0V Timing TDC CPUT and CPUC Duty Cycle TPERIOD TSKEW TCCJ Differential TR/TF SE- DeltaSlew VCROSS 3V66 TDC TPERIOD THIGH TLOW TR/TF TSKEW Unbuffered TSKEW Buffered TCCJ CPUT and CPUC Period Any CPU to Any CPU Clock Skew CPU Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Absolute Single- ended Rise/Fall Waveform Symmetry Cross Point at 1.0V swing 3V66 Duty Cycle 3V66 Period 3V66 HIGH Time 3V66 LOW Time 3V66 Rise and Fall Times 3V66 to 3V66 Clock Skew 3V66 to 3V66 Clock Skew DRCG Cycle to Cycle Jitter
45 14.85
55 15.3 100 150
45 9.85
55 10.2 100 150
45 7.35
55 7.65 100 150
45 4.85
55 5.1 100 150
% nS pS pS ps ps
15, 16 15, 16 12, 15, 16 12, 16 15, 20 21, 22
175
467 325
175
467 325
175
467 325
175
467 325
510
760
510
760
510
760
510
760
mV
22
45 15.0 4.95 4.55 0.5
55 15.3
45 15.0 4.95 4.55
55 15.3
45 15.0 4.95 4.55
55 15.3
45 15.0 4.95 4.55
55 15.3
% ns ns ns
12, 13 9, 12, 13 23 24 25 12, 13 12, 13 12, 13
2.0 500 250 250
0.5
2.0 500 250 250
0.5
2.0 500 250 250
0.5
2.0 500 250 250
ns ps ps ps
Notes: 20. Measurement taken from differential waveform, from -0.35V to +0.35V. 21. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as "the instantaneous difference between maximum CLK rise (fall) and minimum CLK# fall (rise) time or minimum CLK rise (fall) and maximum CLK# fall (rise) time." This parameter is designed form waveform symmetry. 22. Measured in absolute voltage, i.e., single-ended measurement. 23. THIGH is measured at 2.4V for non-host outputs. 24. TLOW is measured at 0.4V for all outputs. 25. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data sheet).
Document #: 38-07331 Rev. *C
Page 15 of 20
CY28346
AC Parameters (VDD = VDDA = 3.3V 5%, TA = 0C to +70C) (continued)
66 MHz Parameter 66B TDC TR/TF TSKEW TPD TCCJ PCI TDC TPERIOD THIGH TLOW TR/TF TSKEW TCCJ 48MUSB TDC TPERIOD TR/TF TCCJ 48MDOT TDC TPERIOD TR/TF TCCJ REF TDC TPERIOD TR/TF TCCJ Description 66B(0:2) Duty Cycle 66B(0:2) Rise and Fall Times Any 66B to Any 66B Skew 66IN to 66B(0:2) Propagation Delay 66B(0:2) Cycle to Cycle Jitter PCI_F(0:2) PCI (0:6) Duty Cycle PCI_F(0:2) PCI (0:6) Period PCI_F(0:2) PCI (0:6) HIGH Time PCI_F(0:2) PCI (0:6) LOW Time PCI_F(0:2) PCI (0:6) Rise and Fall Times Any PCI Clock to Any PCI Clock Skew PCI_F(0:2) PCI (0:6) Cycle to Cycle Jitter 48MUSB Duty Cycle 48MUSB Period 48MUSB Rise and Fall Times 48MUSB Cycle to Cycle Jitter 48MDOT Duty Cycle 48MDOT Period 48MDOT Rise and Fall Times 48MDOT Cycle to Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter 45 69.84 1.0 45 20.837 0.5 1.0 350 45 1.0 45 30.0 12.0 12.0 0.5 2.0 500 250 2.5 Min. 45 0.5 Max. 55 2.0 175 4.5 100 2.5 100 MHz Min. 45 0.5 Max. 55 2.0 175 4.5 100 2.5 133 MHz Min. 45 0.5 Max. 55 2.0 175 4.5 100 2.5 200 MHz Min. 45 0.5 Max. 55 2.0 175 4.5 100 Unit % ns ps ns ps Notes 12, 13 12, 25 12, 13 12, 13 12, 13, 26 12, 13 9, 12, 13 23 24 25 12, 13 12, 13
55
45 30.0 12.0 12.0 0.5
55
45 30.0 12.0 12.0
55
45 30 12.0 12.0
55
% nS nS nS
2.0 500 250
0.5
2.0 500 250
0.5
2.0 500 250
nS pS ps
55 2.0 350
45 1.0
55 2.0 350
45 1.0
55 2.0 350
45 1.0
55 2.10 350
% ns ns ps
12, 13 12, 13 12, 25 9, 12, 13
20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333
55
45 20.837 0.5
55 1.0 350
45 20.837 0.5
55 1.0 350
45 20.837 0.5
55 1.0 350
% ns ns ps
12, 13 12, 13 12, 13 12, 13
55 71.0 4.0 1000
45 69.84 1.0
55 71.0 4.0 1000
45 69.84 1.0
55 71.0 4.0 1000
45 69.84 1.0
55 71.0 4.0 1000
% ns ns ps
12, 13 12, 13 12, 25 12, 13
Note: 26. This figure is in addition to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500-ps jitter figure is specified.
Document #: 38-07331 Rev. *C
Page 16 of 20
CY28346
AC Parameters (VDD = VDDA = 3.3V 5%, TA = 0C to +70C) (continued)
66 MHz Parameter TPZL/TPZH TPZL/TPZH TSTABLE TSS TSH TSU Description Output Enable Delay (All Outputs) Output disable delay (all outputs) All Clock Stabilization from Power-up Stopclock Set-up Time Stopclock Hold Time Oscillator Start-up Time 10.0 0 X Min. 1.0 1.0 Max. 10.0 10.0 3 10.0 0 X 100 MHz Min. 1.0 1.0 Max. 10.0 10.0 3 10.0 0 X 133 MHz Min. 1.0 1.0 Max. 10.0 10.0 3 10.0 0 X 200 MHz Min. 1.0 1.0 Max. 10.0 10.0 3 Unit ns ns ms ns ns ms Notes 10 10 10 27 27 28
VID (0:3), SEL (0,1) VTT_PWRGD# PWRGD
VDD Clock Gen Clock State State 0 Off Off
0.2-0.3mS Delay State 1
Wait for VTT_GD#
Sample Sels State 2 State 3 On (Note A)
Clock Outputs Clock VCO
On
Figure 16. VTT_PWRGD# Timing Diagram29[29]
Table 9. Maximum Lumped Capacitive Output Loads Clock PCI Clocks 3V66 (0,1) 66B(0:2) 48MUSB Clock 48MDOT REF Clock Max. Load 30 30 30 20 10 50 Units pF pF pF pF pF pF
Notes: 27. CPU_STP# and PCI _STP# set-up time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock's rising edge 28. When crystal meets minimum 40 device series resistance specification. 29. Device is not affected, VTT_PWRGD# is ignored.
Document #: 38-07331 Rev. *C
Page 17 of 20
CY28346
TP W = L RG ow D#
S1
S2
Delay 0.25mS
Sample Inputs (pins 54,55)
VT
Enable Outputs
VDDA = 2.0V
S0
S3
Power Off
VDD3.3 = Off
Normal Operation
Figure 17. Clock Generator Power-up/Run State Diagram
Ordering Information
Part Number CY28346OC CY28346OCT CY28346ZC CY28346ZCT Lead-free CY28346OXC CY28346OXCT CY28346ZXC CY28346ZXCT Package Type 56-pin SSOP - Tube 56-pin SSOP - Tape and Reel 56-pin TSSOP - Tube 56-pin TSSOP - Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
56-pin SSOP - Tube 56-pin SSOP - Tape and Reel 56-pin TSSOP - Tube 56-pin TSSOP - Tape and Reel
Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
Document #: 38-07331 Rev. *C
Page 18 of 20
CY28346
Package Drawing and Dimensions
56-lead Shrunk Small Outline Package O56
51-85062-*C
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547] 14.097[0.555]
1.100[0.043] MAX.
GAUGE PLANE 0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030]
0.170[0.006] 0.279[0.011]
0.100[0.003] 0.200[0.008]
51-85060-*C
Intel is a registered trademark of Intel Corporation. Dial-a-Frequency and Dial-a-dB are trademarks of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07331 Rev. *C
Page 19 of 20
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28346
Document History Page
Document Title: CY28346 Clock Synthesizer with Differential CPU Outputs Document Number: 38-07331 REV. ECN NO. Issue Date Orig. of Change Description of Change
** *A *B *C
111653 113983 122897 333314
02/21/02 03/08/02 12/26/02 See ECN
DMG DMG RBI RGL
New Data Sheet
Figure 14 changed
Add power up requirements to maximum ratings information Added Lead-free devices
Document #: 38-07331 Rev. *C
Page 20 of 20

▲Up To Search▲

Price & Availability of CY2834605

	To Download CY2834605 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .